`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    22:12:31 02/23/2009 
// Design Name: 
// Module Name:    regfile 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module regfile(Aselect,Dselect,dbus,clk,Bselect,abus,bbus);

parameter N=32;

input [N-1:0] Aselect, Bselect, Dselect, dbus;
input clk;
output [N-1:0] abus, bbus;



bit_reg R[N-1:1]
(
	.clk(clk),
	.dsel(Dselect[N-1:1]),
	.dbus(dbus),
	.Aselect(Aselect[N-1:1]),
	.Bselect(Bselect[N-1:1]),
	.abus(abus),
	.bbus(bbus)
);


bit_buff A0
(
	.sel(Aselect[0]),
	.Qi1(32'b0),
	.bus(abus)
);


bit_buff B0
(
	.sel(Bselect[0]),
	.Qi1(32'b0),
	.bus(bbus)
);

endmodule
